A compiler implementation for the IEEE-1364 Verilog hardware description language
Icarus Verilog is an implementation of the Verilog hardware description language. It supports the 1995, 2001 and 2005 versions of the standard, portions of SystemVerilog, and some extensions.
For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp'' command. For synthesis, the compiler generates netlists in the desired format.
The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2005.
Operating system:Windows 8, Windows 7, Windows Vista, Windows XP, Windows 2000, Windows 98
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Icarus Verilog 0.9.7 
